Skip to content

Projects

Work, with the reasoning attached

Each entry states the problem, what was actually done, and what the result was — including where it fell short.

Antenna2026 Placeholder

24 GHz Microstrip Patch Array

Problem
A short-range radar front end needed roughly 12 dBi of gain in a footprint under 40 mm square, on standard laminate.
Approach
A 2×2 corporate-fed patch array, designed against the transmission-line model, then solved full-wave and tuned on feed inset and element spacing.
Results
  • Simulated gain in the region of 12 dBi
  • Return loss better than 10 dB across the band of interest
  • Element spacing chosen to keep grating lobes out of the visible region
Ansys HFSSMATLABKiCad
Learn the ideas behind this

Photographs and measured plots will be added as this work is documented.

RF2026 Placeholder

LNA Input Matching Study

Problem
Simultaneous noise and power match on a low-noise amplifier input, where the two optima do not coincide.
Approach
Mapped noise circles and available-gain circles on the same chart, then chose a deliberate compromise point and verified it in harmonic balance.
Results
  • Noise figure penalty quantified against the pure noise match
  • Stability verified across the full band, not only in-band
Keysight ADSPython
Learn the ideas behind this

Photographs and measured plots will be added as this work is documented.

PCB2026 Placeholder

Four-Layer RF Board Stack-up

Problem
A mixed-signal board with fast digital edges alongside an RF chain, on a four-layer budget.
Approach
Both inner layers as ground, power routed as wide traces, and a return via beside every signal via crossing a layer.
Results
  • Controlled-impedance traces specified to the fabricator and confirmed on the stack-up drawing
  • No signal crossing a plane split
KiCadField solver
Learn the ideas behind this

Photographs and measured plots will be added as this work is documented.

AI2026 Placeholder

Surrogate Model for Patch Optimisation

Problem
A full-wave solve per design point made an optimisation loop impractically slow.
Approach
Sampled the design space, trained a surrogate on the simulated responses, optimised against the surrogate, and confirmed the winner in the full solver.
Results
  • Optimisation loop time reduced by orders of magnitude
  • Surrogate predictions checked against full solves before being trusted
Pythonscikit-learnAnsys HFSS
Learn the ideas behind this

Photographs and measured plots will be added as this work is documented.